A novel analogue CMOS design of a cortical cell, that computes weighted sum of inputs, is
presented. The cell's feedback regime exploits the adaptation dynamics of floating gate p
FET 'synapse'to perform competitive learning amongst input weights as time-staggered
winner take all. A learning rate parameter regulates adaptation time and a bias enforces
resource limitation by restricting the number of input branches and winners in a competition.
When learning ends, the cell's response favours one input pattern over others to exhibit …